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ADE7880
Data Sheet
Bit
3
Mnemonic
SUM1SIGN
Default Value
0
Description
0: if the sum of all phase powers in the CF1 data path is positive.
1: if the sum of all phase powers in the CF1 data path is negative. Phase powers in the CF1
data path are identified by Bits[2:0] (TERMSEL1[x]) of the COMPMODE register and by
Bits[2:0] (CF1SEL[x]) of the CFMODE register.
4
AFVARSIGN
0
0: if the fundamental reactive power on Phase A is positive.
1: if the fundamental reactive power on Phase A is negative.
5
BFVARSIGN
0
0: if the fundamental reactive power on Phase B is positive.
1: if the fundamental reactive power on Phase B is negative.
6
CFVARSIGN
0
0: if the fundamental reactive power on Phase C is positive.
1: if the fundamental reactive power on Phase C is negative.
7
SUM2SIGN
0
0: if the sum of all phase powers in the CF2 data path is positive.
1: if the sum of all phase powers in the CF2 data path is negative. Phase powers in the CF2
data path are identified by Bits[5:3] (TERMSEL2[x]) of the COMPMODE register and by
Bits[5:3] (CF2SEL[x]) of the CFMODE register.
8
SUM3SIGN
0
0: if the sum of all phase powers in the CF3 data path is positive.
1: if the sum of all phase powers in the CF3 data path is negative. Phase powers in the CF3
data path are identified by Bits[8:6] (TERMSEL3[x]) of the COMPMODE register and by
Bits[8:6] (CF3SEL[x]) of the CFMODE register.
15:9
Reserved
000 0000
Reserved. These bits are always 0.
Table 47. CONFIG Register (Address 0xE618)
Bit
0
Mnemonic
INTEN
Default Value
0
Description
This bit manages the integrators in the phase current channels.
If INTEN=0, then the integrators in the phase current channels are always disabled.
If INTEN=1, then the integrators in the phase currents channels are enabled.
The neutral current channel integrator is managed by Bit 3 (ININTEN ) of CONFIG3 register.
1
2
Reserved
CF2DIS
1
0
Reserved. This bit should be maintained at 1 for proper operation.
When this bit is cleared to 0, the CF2 functionality is chosen at CF2/HREADY pin.
When this bit is set to 1, the HREADY functionality is chosen at CF2/HREADY pin.
3
SWAP
0
When this bit is set to 1, the voltage channel outputs are swapped with the current channel
outputs. Thus, the current channel information is present in the voltage channel registers
and vice versa.
4
MOD1SHORT
0
When this bit is set to 1, the voltage channel ADCs behave as if the voltage inputs were put
to ground.
5
MOD2SHORT
0
When this bit is set to 1, the current channel ADCs behave as if the voltage inputs were put
to ground.
6
HSDCEN
0
When this bit is set to 1, the HSDC serial port is enabled and HSCLK functionality is chosen at
CF3/HSCLK pin.
When this bit is cleared to 0, HSDC is disabled and CF3 functionality is chosen at CF3/HSCLK pin.
7
9:8
SWRST
VTOIA[1:0]
0
00
When this bit is set to 1, a software reset is initiated.
These bits decide what phase voltage is considered together with Phase A current in the
power path.
00 = Phase A voltage.
01 = Phase B voltage.
10 = Phase C voltage.
11 = reserved. When set, the ADE7880 behaves like VTOIA[1:0] = 00.
11:10
VTOIB[1:0]
00
These bits decide what phase voltage is considered together with Phase B current in the
power path.
00 = Phase B voltage.
01 = Phase C voltage.
10 = Phase A voltage.
11 = reserved. When set, the ADE7880 behaves like VTOIB[1:0] = 00.
Rev. A| Page 98 of 104
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